Define the architecture of the SoC based on application requirements in coordination with internal multi-functional teams like system, software, and digital design;
Define a SoC subsystems including interconnects, busses and interfaces;
Define top-level system and block-level specifications;
Implement and verify optimal design modules leading to FPGA emulation and ASIC implementation;
Implement test benches including checkers, reference models, and coverage groups in SystemVerilog;
Work closely with design, verification, physical design teams to model and build the SoC;
Support post silicon bring-up and debug activities.
S. or PhD in relevant fields
5+ years of experience in the area of digital SoCs, preferably in advanced CMOS technology;
Solid experience in RTL coding and verification;
Deep understanding of ASIC/SoC micro-architecture;
Extensive knowledge of HW/SW partitioning in SoCs;
Experience in interconnect protocols like AHB/AXI/ACE/ACE-Lite;
Experience in design convergence cycle involving architecture, micro architecture, synthesis, DFT, timing closure and verification;
Strong communication and documentations skills.
8+ years of direct experience in ASIC or chip design, with significant hands on experience in architecture and microarchitecture,
SoC-level chip design experience including modern CAD tools;
Solid experience in DDR protocols as well as familiarity with cache interfaces/protocols •
Comfortable working with and managing 3rd party teams.
Experience of programming in a high-level language like C++, or C.
About DiDi Labs
DiDi is a ride-sharing platform dedicated to revolutionizing the way people live and move.
Didi Chuxing offers a full range of on-demand mobility options, including Taxi hailing, private car hailing, Hitch (social ride-sharing), Chauffeur (designated driver), Bus, Minibus, Car Rental, and Enterprise Solutions.
Our company is committed to working with communities and partners to solve the world’s transportation and environmental challenges using big data-driven deep-learning algorithms that optimize resource allocation.